The present invention relates to microelectronic devices and their fabrication.
In system-on-a-chip (SoC) technology, various electronic units are integrated together on a single semiconductor chip. Each semiconductor chip is a microelectronic element obtained by severing a semiconductor wafer into individual chips. Such microelectronic element may have multiple levels of memory caches, where each level of cache has different requirements. For example, a level 2 (L2) cache usually requires high-performance (high speed of access or high data rate); while a level 3 (L3) cache typically requires dense, low-power memory. Capacitors play a significant role in memory performance. For this reason, it is desirable for a semiconductor chip to have different sizes of capacitors to meet different device requirements.
Current methods for fabricating different size capacitors on the same chip can contribute to process complexity and cost of production. It would be desirable to use a combined process to simultaneously fabricate capacitors having differences in size and capacitance values.